(a) Field of the Invention
The present invention relates to a differential amplifier circuit arrangement of the type that the input impedance thereof is stabilized.
(b) Description of the Prior Art
A typical example of differential amplifier circuit arrangement according to the prior art is shown in FIG. 1, which is comprised of a pair of field effect transistors Q.sub.1 and Q.sub.2. These field effect transistors Q.sub.1 and Q.sub.2, which are shown as N-channel type transistors in the Figure, have their sources connected together to a negative power supply line 2 via a constant current source 1, and their drains connected to a positive power supply line 5 via drain load resistors 3 and 4, respectively. This type of differential amplifier circuit arrangement has been widely used, for example, in the input stage circuit of an audio amplifier, wherein an input audio signal is delivered to a terminal 6 connected to the gate of the field effect transistor Q.sub.1, while a certain reference voltage is supplied to a terminal 7 connected to the gate of the other field effect transistor Q.sub.2. In this instance, the output of the differential amplifier is ordinarily taken out at a terminal 8 led from the drain of the field effect transistor Q.sub.1.
With such known circuit arrangement of differential amplifier, the drain-source voltage of the field effect transistor Q.sub.1 undergoes fluctuations in substantial amount in accordance with the input signal applied to the gate of this transistor Q.sub.1, which in turn causes corresponding changes in the drain-gate leakage current I.sub.DGX and also in the common-source short-circuit reverse transfer capacitance C.sub.rss of the transistor Q.sub.1. This means that the input impedance of the differential amplifier as viewed from the terminal 6 changes in response to the input signal applied thereto. If, therefore, a signal source with a relatively high impedance is connected to the terminal 6, the amplified input signal, i.e. the output signal delivered at the terminal 8, is undesirably subjected to non-linear distortion due to the variation of the input impedance of the differential amplifier.
In order to obviate the foregoing problem associated with the fluctuations of input impedance, such differential amplifier circuit arrangement as shown in FIG. 2 has been proposed, in which a cascode bootstrap circuit 11 is additionally provided for stabilizing the drain-source voltages of both field effect transistors Q.sub.1 and Q.sub.2. This cascode bootstrap circuit 11 comprises a pair of npn-type bipolar transistors Q.sub.3 and Q.sub.4 connected in cascode configuration to the drain circuits of the field effect transistors Q.sub.1 and Q.sub.2, respectively. That is, the emitters of the bipolar transistors Q.sub.3 and Q.sub.4 are connected to the drains of the field effect transistors Q.sub.1 and Q.sub.2, respectively, and the collectors of the bipolar transistors Q.sub.3 and Q.sub.4 are connected to the positive power supply line 5 via the drain load resistors 3 and 4, respectively. Also, the bases of these bipolar transistors Q.sub.3 and Q.sub.4 are connected to a jointing point of a series connection of resistors 9 and 10 between the positive power supply line 5 and the mutually coupled sources of the field effect transistors Q.sub.1 and Q.sub.2. In this circuit arrangement, the potential of the respective bases of the bipolar transistors Q.sub.3 and Q.sub.4 is maintained substantially constant relative to the sources of the field effect transistors Q.sub.1 and Q.sub.2, so that the drain-source voltages of the field effect transistors Q.sub.1 and Q.sub.2 are stabilized at an almost constant value independently of the input signal applied to the terminal 6. Accordingly, the aforementioned problem resulting from fluctuating input impedance can be eliminated. However, this known differential amplifier circuit has the disadvantage that it is rather complicated in configuration and costly because of the insertion, in the amplifier circuitry, of said transistor Q.sub.4 which does not contribute to stabilization of the input impedance of the input terminal 6.